Storage systems, AI infrastructure, and the occasional strong opinion.
For 40 years, the CPU decided what gets read from storage, when, and where it lands in memory. AI inference is breaking that model. The GPU now knows what data it needs next, and routing that request through the CPU is pure overhead. GPU-initiated I/O is the architectural response. But the protocol stack wasn't designed for it.
For 40 years, the memory hierarchy was a clean staircase: registers, L1, L2, L3, DRAM, SSD, disk. CXL inserts a new step between DRAM and SSD. Pooled, shared, hardware-coherent memory at 150-400 nanoseconds. For storage systems, it means shared metadata without consensus and memory pools that eliminate stranded DRAM.
NVMe over Fabrics was supposed to make remote flash indistinguishable from local flash. Six years in, TCP added latency nobody budgeted for, RDMA requires a network engineering PhD, and half the industry is deploying NVMe-oF without understanding what they're buying.